Error (10228):Verilog HDL error at top.v(1):module "top" cannot be declared more than once晕

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Error(10228):VerilogHDLerrorattop.v(1):module"top"cannotbedeclaredmorethanonce晕Error(10228):VerilogH

Error (10228):Verilog HDL error at top.v(1):module "top" cannot be declared more than once晕
Error (10228):Verilog HDL error at top.v(1):module "top" cannot be declared more than once

Error (10228):Verilog HDL error at top.v(1):module "top" cannot be declared more than once晕
貌似 叫top 的module 被命名了不知一次